Driving method of variable resistance element, initialization method of variable resistance element, and nonvolatile storage device

ABSTRACT

A method of driving a variable resistance element includes: a writing step performed by applying a writing voltage pulse having a first polarity to a variable resistance layer to change a resistance state of the layer from high to low; and an erasing step performed by applying an erasing voltage pulse having a second polarity to the layer to change the state from low to high. Here, |Vw 1 |&gt;|Vw 2 | where Vw 1  represents a voltage value of the writing voltage pulse for first to N-th writing steps (N≧1) and Vw 2  represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, and |Ve 1 |&gt;|Ve 2 | where Ve 1  represents a voltage value of the erasing voltage pulse for first to M-th erasing steps (M≧1) and Ve 2  represents a voltage value of the erasing voltage pulse for (M+1)-th and subsequent erasing steps. The (N+1)-th writing step follows the M-th erasing step.

TECHNICAL FIELD

The present invention relates to a method of driving a variableresistance element having resistance values that vary depending onapplied electric pulses, an initialization method of the above variableresistance element, and a nonvolatile storage device that performs themethods.

BACKGROUND ART

In recent years, with the development of digital technologies regardingelectronic devices, in order to store data such as images, requirementsarise for a larger capacity of nonvolatile variable resistance elements,reduction of power consumption for writing, a higher speed for awriting/reading time, a longer duration, and the like. It is consideredthat current attempt at more microfabricated flash memories usingfloating gates has a limit to satisfy such requirements.

One conventional technology, which is hereinafter, referred to as“conventional technology 1”, having a possibility of satisfying therequirements is disclosed to provide a nonvolatile variable resistanceelement made of a perovskite material (for example,Pr_((1-x))Ca_(x)MnO₃[PCMO], LaSrMnO₃[LSMO], GdBaCo_(x)O_(y)[GBCO], andthe like) (refer to Patent Reference 1). In this technology, theperovskite material is applied with electric pulses (voltages havingwaveforms with short durations) having different polarities in order toincrease or decrease a resistance value of the material, which enablesthe nonvolatile variable resistance element to store data in associationwith the varying resistance value.

There is another conventional technology, which is hereinafter, referredto as “conventional technology 2”, for switching a resistance value byusing electric pulses having the same polarity. In the technology, anonvolatile variable resistance element exploits the characteristicsthat a resistance value of a film made of transition metal oxide (NiO,V₂O, ZnO, Nb₂O₅, TiO₂, WO₃, or CoO) is varied when electric pulseshaving different pulse widths are applied to the film (refer to PatentReference 2). There is also a variable resistance element made of atransition metal oxide film which has a structure including across-point type memory array using a diode.

PRIOR ARTS Patent Reference

-   [Patent Reference 1] U.S. Pat. No. 6,204,139-   [Patent Reference 2] Japanese Unexamined Patent Application    Publication No. 2004-363604

DISCLOSURE OF INVENTION Problems that Invention is to Solve

However, it is known that conventional technology 1 has a problem ofinsufficiency in operation stability and reproducibility. In addition,since crystallization of an oxide crystal having a perovskite structuresuch as (Pr_(0.7)Ca_(0.3)MnO₃) needs a high temperature generally from650 degrees to 850 degrees, the crystallization used in manufacture of asemiconductor device deteriorates other materials.

Conventional technology 2 also has a problem of a great difficulty inachieving high-speed operation because a pulse width of a voltage forchanging a resistance value from a low resistance state to a highresistance state is considerably long that is 1 msec or more. Therefore,variable resistance elements with stable and high-speed operation aredesired.

The present invention addresses the above-described problems. A primaryobject of the present invention is to provide a variable resistanceelement driving method of driving a variable resistance element withstability and at a high speed, and a nonvolatile storage device that canperform the method.

Means to Solve the Problems

In accordance with an aspect of the present invention for achieving theobject, there is provided a method of driving a variable resistanceelement that includes a metal oxide having resistance values increasedand decreased depending on application of electric pulses, the metaloxide including a first oxide layer and a second oxide layer which arestacked, the second oxide layer having an oxygen content percentagehigher than an oxygen content percentage of the first oxide layer, themethod including: performing a plurality of writing steps by applying awriting voltage pulse having a first polarity to the metal oxide, so asto change a resistance state of the metal oxide from high to low; andperforming a plurality of erasing steps by applying an erasing voltagepulse having a second polarity to the metal oxide, so as to change theresistance state of the metal oxide from low to high, the secondpolarity being different from the first polarity, wherein |Vw1|>|Vw2| issatisfied, where Vw1 represents a voltage value of the writing voltagepulse for first to N-th writing steps among the plurality of writingsteps, where N is equal to or more than 1, and Vw2 represents a voltagevalue of the writing voltage pulse for (N+1)-th and subsequent writingsteps among the plurality of writing steps, |Ve1|>|Ve2| is satisfied,where Ve1 represents a voltage value of the erasing voltage pulse forfirst to M-th erasing steps among the plurality of erasing steps, whereM is equal to or more than 1, and Ve2 represents a voltage value of theerasing voltage pulse for (M+1)-th and subsequent writing steps amongthe plurality of erasing steps, and the (N+1)-th writing step followsthe M-th erasing step.

In the above-described method according to the aspect, it is preferablethat |Ve1|≧|Vw1| and |Ve2|≧|Vw2| are further satisfied.

In the above-described method according to the aspect, it is alsopreferable that the method further includes: performing a recoverywriting step by applying a recovery writing voltage pulse having avoltage value of Vw3, where |Vw3|>|Vw2|, to the metal oxide, so as tochange the resistance state of the metal oxide from high to low, whenany one of the (N+1)-th and subsequent writing steps fails to change theresistance state of the metal oxide from high to low; and performing arecovery erasing step by applying a recovery erasing voltage pulsehaving a voltage value of Ve3, where |Ve3|>|Ve2|, to the metal oxide, soas to change the resistance state of the metal oxide from low to high,when any one of the (M+1)-th and subsequence erasing steps fails tochange the resistance state of the metal oxide from low to high.

In the above-described method according to the aspect, it is furtherpreferable that the voltage value of Vw1 is equal to the voltage valueof Vw3, and the voltage value of Ve1 is equal to the voltage value ofVe3.

In the above-described method according to the aspect, it is stillfurther preferable that the first oxide layer comprises a tantalum oxidehaving a composition represented by TaO_(x), where 0.8≦x≦1.9, and thesecond oxide layer comprises a tantalum oxide having a compositionrepresented by TaO_(y), where 2.1≦y<2.5.

In accordance with another aspect of the present invention, there isprovided a nonvolatile storage device including: a first electrode; asecond electrode; a variable resistance element which is providedbetween the first electrode and the second electrode and which includesa metal oxide having a resistance value increased and decreaseddepending on application of electric pulses between the first electrodeand the second electrode; and a drive unit, wherein the metal oxideincludes a first oxide layer and a second oxide layer which are stacked,the second oxide layer having an oxygen content percentage higher thanan oxygen content percentage of the first oxide layer, and the driveunit is configured to perform: a writing step by applying a writingvoltage pulse having a first polarity between the first electrode andthe second electrode, so as to change a resistance state of the metaloxide from high to low; and an erasing step by applying an erasingvoltage pulse having a second polarity between the first electrode andthe second electrode, so as to change the resistance state of the metaloxide from low to high, the second polarity being different from thefirst polarity, wherein |Vw1|>|Vw2| is satisfied, where Vw1 represents avoltage value of the writing voltage pulse for first to N-th writingsteps, where N is equal to or more than 1, and Vw2 represents a voltagevalue of the writing voltage pulse for (N+1)-th and subsequent writingsteps, |Ve1|>|Ve2| is satisfied, where Ve1 represents a voltage value ofthe erasing voltage pulse for first and M-th erasing steps, where M isequal to or more than 1, and Vet represents a voltage value of theerasing voltage pulse for (M+1)-th and subsequent erasing steps, and the(N+1)-th writing step follows the M-th erasing step.

In the above-described nonvolatile storage device according to theaspect, it is preferable that |Ve1|≧|Vw1| and |Ve2|≧|Vw2| are furthersatisfied.

In the above-described nonvolatile storage device according to theaspect, it is also preferable that the drive unit is configured tofurther perform: a recovery writing step by applying a recovery writingvoltage pulse having a voltage value of Vw3, where |Vw3|>|Vw2|, betweenthe first electrode and the second electrode, so as to change theresistance state of the metal oxide from high to low, when any one ofthe (N+1)-th and subsequence writing steps fails to change theresistance state of the metal oxide from high to low; and a recoveryerasing step by applying a recovery erasing voltage pulse having avoltage value of Ve3, where |Ve3|>|Ve2|, between the first electrode andthe second electrode, so as to change the resistance state of the metaloxide from low to high, when any one of the (M+1)-th and subsequenterasing step fails to change the resistance state of the metal oxidefrom low to high.

In the above-described nonvolatile storage device according to theaspect, it is further preferable that the voltage value of Vw1 is equalto the voltage value of Vw3, and the voltage value of Ve1 is equal tothe voltage value of Ve3.

In the above-described nonvolatile storage device according to theaspect, it is still further preferable that the first oxide layercomprises a tantalum oxide having a composition represented by TaO_(x),where 0.8≦x≦1.9, and the second oxide layer comprises a tantalum oxidehaving a composition represented by TaO_(y), where 2.1≦y<2.5.

In the above-described nonvolatile storage device according to theaspect, it is still further preferable that the nonvolatile storagedevice further includes a current steering element electricallyconnected to one of the first electrode and the second electrode. Thecurrent steering element may be a selection transistor. The currentsteering element may be a diode.

In accordance with still another aspect of the present invention, thereis provided an initialization method of performing initialization for avariable resistance element which includes a metal oxide having aresistance value increased and decreased depending on application ofelectric pulses, the metal oxide including a first oxide layer and asecond oxide layer which are stacked, the second oxide layer having anoxygen content percentage higher than an oxygen content percentage ofthe first oxide layer, to and from the variable resistance element, databeing written and erase by performing one or more times a set of awriting step and an erasing step so as to perform at least one writingstep and at least one erasing steps, the writing step being performed byapplying a writing voltage pulse having a first polarity and a voltagevalue of Vw2 to the metal oxide, so as to change a resistance state ofthe metal oxide from high to low, and the erasing step being performedby applying an erasing voltage pulse having a second polarity and avoltage value of Ve2 to the metal oxide, so as to change the resistancestate of the metal oxide from low to high, the second polarity beingdifferent from the first polarity, and the erasing step following thewriting step, the method including: at least one initial writing step byapplying a voltage pulse having the first polarity and a voltage valueof Vw1, where |Vw1|>|Vw2|, to the metal oxide, so as to change theresistance state of the metal oxide from high to low; and at least oneinitial erasing step by applying a voltage pulse having the secondpolarity and a voltage value of Ve1, where |Ve1|>|Ve2|, to the metaloxide, so as to change the resistance state of the metal oxide from lowto high, wherein a first one of the at least one writing step isperformed next to a last one of the at least one initial erasing step.

Effects of the Invention

The method of driving a variable resistance element according to thepresent invention can vary a resistance of a variable resistance elementwith stability and at a high speed. In addition, the nonvolatile storagedevice that performs the method according to the present invention canbe implemented as a storage device that can operate with stability andat a high speed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram showing an example of a structure of avariable resistance element according to the first embodiment of thepresent invention.

FIG. 2 is a flowchart of steps of a method of driving the variableresistance element according to the first embodiment of the presentinvention.

FIG. 3 is a graph plotting an example of variation of a resistance stateof a variable resistance layer.

FIG. 4 is a diagram showing an example of a structure of a circuitoperating the variable resistance element and an operation example ofthe case where data is written to the variable resistance elementaccording to the first embodiment of the present invention.

FIG. 5 is a graph plotting variation of a resistance value of thevariable resistance layer in the case where data is written to anderased from the variable resistance element according to the firstembodiment of the present invention.

FIG. 6 is a diagram showing an example of a structure of a circuitoperating the variable resistance element and an operation example ofthe case where data is read out from the variable resistance elementaccording to the first embodiment of the present invention.

FIG. 7 is a graph plotting a relationship between (a) a current value ofcurrent flowing in a circuit having the variable resistance element and(b) a resistance value of a variable resistance layer, when data is readout, according to the first embodiment of the present invention.

FIG. 8A is a graph plotting hysteresis characteristics of variation of aresistance value of a variable resistance layer 3 in the case where thevariable resistance element is applied with plural different electricpulses by sequentially varying a voltage value, according to the firstembodiment of the present invention.

FIG. 8B is a graph plotting hysteresis characteristics of anothervariable resistance element which is manufactured to have a differentthickness of the variable resistance layer.

FIG. 9 is a graph plotting a result of examination for quality ofendurance characteristics in the case of |Ve1|>|Ve2|.

FIG. 10 is a graph plotting a result of examination for quality ofendurance characteristics in the case of |Ve1|≦|Ve2|.

FIG. 11 is a graph plotting variation of a resistance state of avariable resistance layer included in a variable resistance element in afirst comparative example, in the case where a voltage value of a firstwriting voltage pulse and a voltage value of a second writing voltagepulse are the same −2.0 V and a voltage value of a first erasing voltagepulse and a voltage value of a second erasing voltage pulse are the same+2.5 V.

FIG. 12 is a graph plotting variation of a resistance state of avariable resistance layer included in a variable resistance element in asecond comparative example, in the case where a voltage value of a firstwriting voltage pulse and a voltage value of a second writing voltagepulse are the same −2.5 V and a voltage value of a first erasing voltagepulse and a voltage value of a second erasing voltage pulse are the same+3.5 V.

FIG. 13 is a graph plotting an example of variation of a resistancestate of a variable resistance layer included in a variable resistanceelement according to a second embodiment of the present invention.

FIG. 14 is a flowchart of steps of a method of driving the variableresistance element according to the second embodiment of the presentinvention.

FIG. 15 is a block diagram showing an example of a structure of anonvolatile storage device according to a third embodiment of thepresent invention.

FIG. 16 is a block diagram showing an example of a structure of anonvolatile storage device according to a fourth embodiment of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The following describes preferred embodiments according to the presentinvention with reference to the drawings.

First Embodiment Structure of Variable Resistance Element

First, a structure of a variable resistance element according to thefirst embodiment is described.

FIG. 1 is a schematic diagram showing an example of the structure of thevariable resistance element according to the first embodiment of thepresent invention. As shown in FIG. 1, the variable resistance element10 according to the first embodiment includes a substrate 1, a lowerelectrode 2 formed on the substrate 1, a variable resistance layer 3formed on the lower electrode 2, an upper electrode 4 formed on thevariable resistance layer 3. Each of the lower electrode 2 and the upperelectrode 4 is electrically connected to the variable resistance layer3.

The substrate 1 comprises a silicon substrate, for example. Each of thelower electrode 2 and the upper electrode 4 comprises at least one ofmaterials gold (Au), platinum (Pt), iridium (Ir), and copper (Cu).

The variable resistance layer 3 comprises a first tantalum oxide layer 3a and a second tantalum oxide layer 3 b which are stacked sequentially.Here, an oxygen content percentage of the second tantalum oxide layer 3b is higher than an oxygen content percentage of the first tantalumoxide layer 3 a.

A resistance value of the variable resistance layer 3 can be varied,with stability and at a high speed, in the following situation. Assuminga composition of the first tantalum oxide layer 3 a is TaO_(x), x iswithin a range from 0.8 to 1.9, and assuming a composition of the secondtantalum oxide layer 3 b is TaO_(y), y is within a range from 2.1 to2.5. Therefore, it is preferable that x and y are within the aboverespective ranges.

Although a resistance value is varied if a thickness of the variableresistance layer 3 is 1 μm or less, the thickness is preferably equal toor less than 200 nm. This is because the thickness of 200 nm or less canfacilitate manufacturing if lithography is used as a patterning process,and can lower a voltage value of a voltage pulse necessary to change aresistance value of the variable resistance layer 3. On the other hand,in order to surely prevent a breakdown (insulation breakdown) inapplication of a voltage pulse, a thickness of the variable resistancelayer 3 is preferably at least 5 nm or more.

Regarding a thickness of the second tantalum oxide layer 3 b, if thethickness is too large, there are drawbacks such as too high initialresistance value, and if too small, there are drawbacks of unstableresistance variation, for example. Therefore, the thickness of thesecond tantalum oxide layer 3 b is preferably within a rangeapproximately from 1 nm to 8 nm.

When the variable resistance element 10 having the above-describedstructure is to be operated, the lower electrode 2 and the upperelectrode 4 are electrically connected to respective different terminalsof a power source 5. The power source 5, which serves as an electricpulse applying device that drives the variable resistance element 10,has a structure for applying electric pulses (voltage pulses) havingpredetermined polarities, voltages, and time widths between the lowerelectrode 2 and the upper electrode 4.

It is assumed in the following description that a voltage of a voltagepulse applied between the electrodes is determined by a potential of theupper electrode 4 with reference to the lower electrode 2.

[Manufacturing Method of Variable Resistance Element]

Next, a method of manufacturing the variable resistance element 10 isdescribed.

First, the lower electrode 2 having a thickness of 0.2 μm is formed onthe substrate 1 by a sputtering method. Then, using a so-called reactivesputtering method for spattering a Ta target in argon gas and oxygengas, a tantalum oxide layer is formed on the lower electrode 2. Here, anoxygen content percentage of the tantalum oxide layer can be easilyadjusted by changing a ratio of a flow rate of the oxygen gas to a flowrate of the argon gas. The temperature of the substrate can be set as anambient temperature, and heating is not necessary.

Next, a top surface of the tantalum oxide layer formed in the abovemanner is oxidized to be improved. Thereby, on the surface of thetantalum oxide layer has a range (second range) having an oxygen contentpercentage that is higher than that of the other range (first range) inwhich the oxidization is not applied. The first range corresponds to thefirst tantalum oxide layer 3 a and the second range corresponds to thesecond tantalum oxide layer 3 b. The first tantalum oxide layer 3 a andthe second tantalum oxide layer 3 b which are manufactured in the abovemanner form the variable resistance layer 3.

Next, on the variable resistance layer 3 generated in the above manner,the upper electrode 4 having a thickness of 0.2 μm is formed by asputtering method. As a result, the variable resistance element 10 ismanufactured.

Here, a size and a shape of each of the lower electrode 2, the upperelectrode 4, and the variable resistance layer 3 can be adjusted by amask and a lithography. In the first embodiment, a size of each of theupper electrode 4 and the variable resistance layer 3 is set to be 0.5μm×0.5 μm (an area of 0.25 μm²), and a size of a part where the lowerelectrode 2 contacts the variable resistance layer 3 is set to be thesame 0.5 μm×0.5 μm (an area of 0.25 μm²).

Further, in the first embodiment, the first tantalum oxide layer 3 acomprises a composition represented by TaO_(x) (where x=1.54) and thesecond tantalum oxide layer 3 b comprises a composition represented byTaO_(y) (where y=2.47). Analysis on compositions of the oxide layers inthe embodiments of the present invention always employs RutherfordBackscattering Spectrometry (RBS). Furthermore, a thickness of thevariable resistance layer 3 is set to be 30 nm, a thickness of the firsttantalum oxide layer 3 a is set to be 22 nm, and a thickness of thesecond tantalum oxide layer 3 b is set to be 8 nm.

It should be noted that the description of the first embodiment isgiven, assuming x=1.54 and y=2.47, but the present invention is notlimited to this. If 0.8≦x≦1.9 and 2.1≦y<2.5, stable resistance variationcan be achieved like the variable resistance characteristics in thefirst embodiment.

[Operation of Variable Resistance Element]

The following describes operation of the variable resistance element 10manufactured in the above-described manufacturing method.

In the following description, a high resistance state refers to asituation where a resistance value of the variable resistance layer 3 ishigh (for example, 20000Ω), and a low resistance state refers to asituation where the resistance value is low (for example, 700Ω).

When a writing voltage pulse that is a voltage pulse having a negativepolarity is applied between the lower electrode 2 and the upperelectrode 4 using the power source 5, the resistance value of thevariable resistance layer 3 is decreased and thereby the variableresistance layer 3 is changed from a high resistance state to a lowresistance state. This is called a writing step in the followingdescription.

On the other hand, when an erasing voltage pulse that is a voltage pulsehaving a positive polarity is applied between the lower electrode 2 andthe upper electrode 4 using the power source 5, the resistance value ofthe variable resistance layer 3 is increased and thereby the state ofthe variable resistance layer 3 is changed from a low resistance stateto a high resistance state. This is called an erasing step in thefollowing description.

Here, even if a voltage pulse having a negative polarity that is thesame polarity of the writing voltage pulse is applied between the lowerelectrode 2 and the upper electrode 4 when the variable resistance layer3 is in a low resistance state, the variable resistance layer 3 is notchanged and is still in the low resistance state. Likewise, even if avoltage pulse having a positive polarity that is the same polarity ofthe erasing voltage pulse is applied between the lower electrode 2 andthe upper electrode 4 when the variable resistance layer 3 is in a highresistance state, the variable resistance layer 3 is not changed and isstill in the high resistance state.

By executing a writing step and an erasing step alternately, thevariable resistance element 10 is operated. Here, so-called overwriting,which is successive execution of writing steps or successive executionof erasing steps, may be performed.

In the first embodiment, |Vw1|>|Vw2|, where Vw1 represents a voltagevalue of a writing voltage pulse (hereinafter, referred to as a “firstwriting voltage pulse”) in writing steps (hereinafter, referred to as“first writing steps”) from the first writing step to the N-th writingstep (where N is equal to or more than 1), and Vw2 represents a voltagevalue of a writing voltage pulse (hereinafter, referred to as a “secondwriting voltage pulse”) in writing steps (hereinafter, referred to as“second writing steps”) of and subsequent to the (N+1)-th writing step.

In addition, |Ve1|>|Ve2|, where Ve1 represents a voltage value of anerasing voltage pulse (hereinafter, referred to as a “first erasingvoltage pulse”) in erasing steps (hereinafter, referred to as “firsterasing steps”) from the first erasing step to the M-th erasing step(where M is equal to or more than 1), and Ve2 represents a voltage valueof an erasing voltage pulse (hereinafter, referred to as a “seconderasing voltage pulse”) in erasing steps (hereinafter, referred to as“second erasing steps”) of and subsequent to the (M+1)-th erasing step.

Here, when overwriting is executed from the first writing, in otherwords, when a plurality of the first writing steps are performedsuccessively, N in the above conditions is equal to or more than 2.Likewise, when a plurality of the first erasing steps are performedsuccessively, M in the above conditions is equal to or more than 2.

Moreover, when a first writing step and a first erasing step areexecuted alternately and such execution is repeated, which is differentfrom the above overwriting, each of N and M is equal to or more than 2.

Although each of N and M is equal to or more than 2 as described above,a second writing step should follow a first erasing step whatever N andM are. In other words, it is necessary that there is a first erasingstep between a first writing step and a second writing step, therebypreventing that the first writing step and the second writing step areexecuted successively. If a second writing step does not follow a firsterasing step and the second writing step follows a first writing step,it is difficult to achieve stable resistance variation.

The above-described method of driving the variable resistance element 10according to the first embodiment of the present invention is presentedby a flowchart of FIG. 2. First, a first writing step is executed byapplying a voltage pulse having a voltage value Vw1 (S101). Thereby, thestate of the variable resistance layer 3 is changed from an initial highresistance state (HR) to a low resistance state (LR). Next, a firsterasing step is executed by applying a voltage pulse having a voltagevalue Ve1 (S102). Thereby, the state of the variable resistance layer 3is changed from the low resistance state to a high resistance state.

After that, Step 103 for repeating a pair of a second writing step and asecond erasing step is executed. More specifically, a second writingstep using a voltage pulse having a voltage value Vw2 (S103A) and asecond erasing step using a voltage pulse having a voltage value Vet(S103B) are repeated alternately. The execution of Step S103A changesthe state of the variable resistance layer 3 from a high resistancestate to a low resistance state, while the execution of Step S103Bchanges the state of the variable resistance layer 3 from a lowresistance state to a high resistance state.

As described above, if at least one of N and M in the conditions isequal to or more than 2, at least one of Steps S101 and S102 isrepeated.

The present invention does not limit any details for implementing thesteps in the flowchart of FIG. 2. For instance, Steps S101 and S102 maybe performed before shipment of a manufactured variable resistanceelement, as initialization for the variable resistance element. And,Step S102 may be performed when a user actually uses the variableresistance element (namely, writes or erases data).

As described in more detail later, execution of Steps S101 and S102 fora variable resistance element having an initial resistance state aftermanufacturing can provide the variable resistance element with stablehigh-speed operation and good endurance characteristics. Therefore,Steps S101 and S102 are executed for a variable resistance elementbefore its shipment in order to confirm a desired change in itsresistance state. Thereby, it is possible to perform, at once, theexamination for production quality and the improvement of operationcharacteristics.

FIG. 3 is a graph showing an example of variation of a resistance stateof the variable resistance layer 3. In this example, a voltage value Vw1of the first writing voltage pulse is assumed to be −3.0 V, and avoltage value Vw2 of the second writing voltage pulse is assumed to be−2.0 V. In addition, a voltage value Ve1 of the first erasing voltagepulse is assumed to be +4.0 V, and a voltage value Vet of the secondwriting voltage pulse is assumed to be +2.5 V. Here, in any cases, apulse width is assumed to be 100 ns. It is also assumed in the graphthat a first writing step is executed once and a first erasing step isexecuted once.

FIG. 3 shows stable variation of the resistance state of the variableresistance layer 3. As shown in FIG. 3, application of voltage pulsesbetween the two electrodes satisfying |Vw1|>|Vw2| and |Ve1|>|Ve2| allowsthe variable resistance element 10 to be operated with stability. Thefirst embodiment satisfies also the conditions of |Ve1|≧|Vw1| and|Ve2|≧|Vw2|, which is considered as one of causes of the stableoperation of the variable resistance element 10.

The following describes the situation where the variable resistanceelement 10 is implemented as a memory, to and from which data having onebit is written and read out. In the following case, “1” represents a lowresistance state of the variable resistance layer 3, and “0” representsa high resistance state of the variable resistance layer 3.

FIG. 4 is a diagram showing an example of a structure of a circuitoperating the variable resistance element 10 according to the firstembodiment of the present invention and an operation example of the casewhere data is written to the variable resistance element 10. As shown inFIG. 4, the circuit includes the variable resistance element 10, a firstterminal 11, and a second terminal 12. The upper electrode 4 of thevariable resistance element 10 is electrically connected to the firstterminal 11, and the lower electrode 2 of the variable resistanceelement 10 is electrically connected to the second terminal 12.

FIG. 5 is a graph plotting variation of resistance values of thevariable resistance layer 3 in the case where data is written to(writing step) and erased from (erasing step) the variable resistanceelement 10 according to the first embodiment of the present invention.In the writing step and the erasing step, as shown in FIG. 4, the secondterminal 12 is grounded (GND) and a voltage pulse is provided to thefirst terminal 11. The voltage pulse is determined with reference to thelower electrode 2 and a ground point.

When the variable resistance element 10 is in an initial state (in otherwords, a resistance value of the variable resistance layer 3 is aninitial resistance value), a first writing voltage pulse having anegative polarity (voltage value Vw1) is provided to the first terminal11. Thereby, as shown in FIG. 5, a resistance value of the variableresistance layer 3 is decreased from the initial resistance value andthe variable resistance layer 3 gets in a low resistance state Ra. As aresult, one bit data indicating “1” is written to the variableresistance element 10. Next, when a first erasing voltage pulse having apositive polarity (voltage value Ve1) is provided to the first terminal11, the state of the variable resistance layer 3 is changed from the lowresistance state Ra to a high resistance state Rb. As a result, one bitdata indicating “0” is written to the variable resistance element 10.

Then, if, in the high resistance state Rb of the variable resistancelayer 3, a second writing voltage pulse having a negative polarity(voltage value Vw2) is provided to the first terminal 11, the highresistance state Rb of the variable resistance layer 3 is changed to thelow resistance state Ra. On the other hand, if, in the low resistancestate Ra of the variable resistance layer 3, a second erasing voltagepulse having a positive polarity (voltage value Ve2) is provided to thefirst terminal 11, the low resistance state Ra of the variableresistance layer 3 is changed to the high resistance state Rb.

In the circuit, when a voltage pulse is supplied to the first terminal11 satisfying |Vw1|>|Vw2| and |Ve1|>|Ve2| as described above, thevariable resistance element 10 can serve as a memory in which thevariable resistance element 10 operates with stability and at a highspeed.

FIG. 6 is a diagram showing an example of a structure of a circuitoperating the variable resistance element 10 according to the firstembodiment of the present invention and an operation example of the casewhere data is read out from the variable resistance element 10. As shownin FIG. 6, when data is to be read out, the second terminal 12 isgrounded (GND), and a readout voltage is provided to the first terminal11. The readout voltage is determined with reference to the lowerelectrode 2 and a ground point.

FIG. 7 is a graph plotting a relationship between (a) a current value ofcurrent flowing in a circuit having the variable resistance element 10according to the first embodiment of the present invention and (b) aresistance value of the variable resistance layer 3, when data is readout. When a readout voltage is provided to the first terminal 11,current depending on the resistance value of the variable resistancelayer 3 flows in the circuit. More specifically, as shown in FIG. 7,when the variable resistance layer 3 is in the low resistance state Ra,current having a current value Ia flows in the circuit, while when thevariable resistance layer 3 is in the high resistance state Rb, currenthaving a current value Ib flows in the circuit.

When the second terminal 12 is grounded as shown in FIG. 6 and a readoutvoltage of +0.5 V, for example, is provided to the first terminal 11, acurrent value of the current flowing between the first terminal 11 tothe second terminal 12 is detected to determine whether the variableresistance layer 3 is in the high resistance state or in the lowresistance state. More specifically, if the detected current value isIa, it is determined that the variable resistance layer 3 is in the lowresistance state Ra. As a result, it is learned that data written to thevariable resistance element 10 is “1”. On the other hand, if thedetected current value is Ib, it is determined that the variableresistance layer 3 is in the high resistance state Rb. As a result, itis learned that data written to the variable resistance element 10 is“0”. As described above, data is read out from the variable resistanceelement 10.

A resistance value of the variable resistance element 10 according tothe first embodiment is not changed even if the variable resistanceelement 10 is powered off. Therefore, the variable resistance element 10can be implemented as a nonvolatile storage device.

FIG. 8A is a graph plotting hysteresis characteristics of variation of aresistance value of the variable resistance layer 3 in the case wherethe variable resistance element 10 according to the first embodiment ofthe present invention is applied with plural different electric pulsesby sequentially varying a voltage value. In the variable resistanceelement 10 in the examination, the variable resistance layer 3 has athickness of 30 nm, the first tantalum oxide layer 3 a has a thicknessof 22 nm, and the second tantalum oxide layer 3 b has a thickness of 8nm. A composition of the first tantalum oxide layer 3 a is x=1.54 wheretantalum oxide is expressed as TaO_(x), and a composition of the secondtantalum oxide layer 3 b is y=2.47 where tantalum oxide is expressed asTaO_(y).

As shown in FIG. 8A, while a voltage value of the voltage pulse ischanged from 0 V and reaches approximately −3.0 V, a resistance value ofthe variable resistance layer 3 remains as an initial resistance value.When the voltage value of the voltage pulse reaches a threshold voltageV_(L1) that is approximately −3.0 V, the resistance value isdramatically decreased. Then, while the voltage value of the voltagepulse is changed from approximately −3.0 V to approximately −3.5 V thatis the lowest voltage, and reaches approximately +3.5 V, the resistancevalue of the variable resistance layer 3 remains low. When the voltagevalue reaches a threshold value V_(H1) that is approximately +3.5 V, theresistance value is getting increased. While the voltage value ischanged from the highest voltage that is approximately +4.0 V andreaches approximately +3.3 V, the resistance value of the variableresistance layer 3 is dramatically increased. Then, while the voltagevalue of the voltage pulse is changed from approximately +3.3 V to 0 V,the resistance value of the variable resistance layer 3 remains high.This is track of a “first cycle” shown by black dots in FIG. 8A.

Next, while the voltage value of the voltage pulse is changed from 0 Vand reaches approximately −1.0 V, the resistance value of the variableresistance layer 3 remains high. When the voltage value reaches athreshold voltage V_(L2) that is approximately −1.0 V, the resistancevalue is dramatically decreased. Then, while the voltage value of thevoltage pulse is changed from approximately −1.0 V to approximately −1.5V that is the lowest voltage, and reaches approximately +1.7 V, theresistance value of the variable resistance layer 3 remains low. Whenthe voltage value reaches a threshold value V_(H2) that is approximately+1.7 V, the resistance value is dramatically increased. Then, while thevoltage value is changed from the highest voltage that is fromapproximately +1.7 V to approximately +2.0 V and reaches 0 V, theresistance value of the variable resistance layer 3 remains high. Thisis track of a “second cycle” shown by white dots in FIG. 8A.

Further, while the voltage value of the voltage pulse is changed from 0V and reaches approximately −0.7 V, the resistance value of the variableresistance layer 3 remains high. When the voltage value reaches athreshold voltage V_(L3) that is approximately −0.7 V, the resistancevalue is dramatically decreased. Then, while the voltage value of thevoltage pulse is changed from approximately −0.7 V to approximately −1.5V that is the lowest voltage, and reaches approximately +1.7 V, theresistance value of the variable resistance layer 3 remains low. Whenthe voltage value reaches a threshold value V_(H3) that is approximately+1.7 V, the resistance value is dramatically increased. Then, while thevoltage value is changed from approximately +1.7 V that is the highestvoltage to approximately +2.0 V, and reaches 0 V, the resistance valueof the variable resistance layer 3 remains high. This is track of a“third cycle” shown by black triangles in FIG. 8A. A track of a “fourthcycle” shown by white triangles is the same as the track of the “thirdcycle”.

Furthermore, the same examination is conducted on the variableresistance element 10 that includes the variable resistance layer havinga different thickness. In the variable resistance element with thedifferent thickness, the variable resistance layer 3 has a thickness of50 nm, the first tantalum oxide layer 3 a has a thickness of 45 nm, andthe second tantalum oxide layer 3 b has a thickness of 5 nm. Acomposition of the first tantalum oxide layer 3 a is x=1.54 wheretantalum oxide is expressed as TaO_(x), and a composition of the secondtantalum oxide layer 3 b is y=2.47 where tantalum oxide is expressed asTaO_(y).

FIG. 8B is a graph plotting hysteresis characteristics of the abovevariable resistance element. Although characteristics of the variableresistance element of FIG. 8B differs from that of the variableresistance element 10 regarding FIG. 8A in a value of each thresholdvalue voltage, both characteristics show similar forms in the graphs.

Results of plural examinations including results of FIGS. 8A and 8B showthat hysteresis characteristics of a variable resistance element has thefollowing general properties.

(i) An absolute value of a threshold value voltage V_(Ln) that causes aresistance change to low resistance state in the variable resistancelayer in the n-th cycle (where n is equal to or more than 1) is maximumin the first cycle where the variable resistance layer is in the initialresistance state, and is decreased in and after the second cycle.

(ii) In each cycle, an absolute value of a threshold value voltageV_(Hn) that produces a high resistance state of the variable resistancelayer is equal to or greater than an absolute value of a minimum voltageof a voltage pulse having a negative polarity that is applied to achievea low resistance state of the variable resistance layer in thecorresponding cycle.

In FIG. 8A, although a resistance value of the variable resistance layerwith a threshold value voltage V_(H1) in the first cycle is gettingincreased, the variable resistance layer is not immediately changed tohave a high resistance state. Later observation shows that the aboverelates to a protection resistance inserted in series in the examinationcircuit. When a value of the protection resistance is selectedappropriately depending on a thickness of the variable resistance layer,hysteresis characteristics plotted in the graph of FIG. 8B, for example,are obtained.

The above-described results show that a first writing step and a firsterasing step can be executed when, according to the voltage valuehysteresis characteristics of FIG. 8A for example, a voltage value Vw1of a first writing voltage pulse is set to be −3.5 V that is lower thanthe threshold value voltage V_(L1) of approximately −3.0 V and a voltagevalue Ve1 of a first erasing voltage pulse is set to be approximately+4.0 V that is higher than the Vw1.

In addition, since |V_(L1)>|V_(L2)| and |V_(H1)|>|V_(H2)|, it isappropriate that a voltage value Vw2 of a second writing voltage pulseis set to be within a range approximately from −0.7 V to −2.5 V and thata voltage value Ve2 of a second erasing voltage pulse is set to bewithin a range approximately from +1.7 V to +3.5 V, in order to satisfythe conditions |Vw1|>|Vw2| and |Ve1|>|Ve2|. Therefore, as describedpreviously with reference to FIG. 2, in the first embodiment, Vw1 is setto be −3.0 V, Vw2 is set to be −2.0 V, Ve1 is set to be +4.0 V, and Ve2is set to be +2.5 V.

Next, how a size relationship among voltage values of respective voltagepulses influences endurance characteristics of the variable resistanceelement is described.

FIG. 9 is a graph plotting a result of examination for quality ofendurance characteristics in the case of |Ve1|>|Ve2|. FIG. 10 is a graphplotting a result of examination for quality of endurancecharacteristics in the case of |Ve1|≦|Ve2|. In the graphs, if a stableresistance variation is repeated one hundred times, then endurancecharacteristics are determined as good (shown by circles), andotherwise, endurance characteristics are determined as not good (shownby X marks).

As shown in FIG. 9, if both |Ve1|>|Ve2| and |Vw1|>|Vw2| are satisfied,endurance characteristics are good. On the other hand, as shown in FIGS.9 and 10, if at least one of |Ve1|>|Ve2| and |Vw1|>|Vw2| is notsatisfied, endurance characteristics are not good.

The variable resistance element 10 according to the first embodimentsatisfies both |Ve1|>|Ve2| and |Vw1|>|Vw2|. Therefore, the results ofthe above examination prove that the variable resistance element 10according to the first embodiment has good endurance characteristics.

First Comparative Example

The following describes a variable resistance element according to afirst comparative example. A structure of the variable resistanceelement according to the first comparative example is the same as thatof the variable resistance element 10 in the first embodiment.Therefore, the structure of the variable resistance element is notdescribed below.

FIG. 11 is a graph plotting variation of a resistance state of avariable resistance layer included in the variable resistance elementaccording to the first comparative example in the case where both avoltage value Vw1 of a first writing voltage pulse and a voltage valueVw2 of a second writing voltage pulse are the same −2.0 V and both avoltage value Ve1 of a first erasing voltage pulse and a voltage valueVe2 of a second erasing voltage pulse are the same +2.5 V. Here, in anycases, a pulse width is assumed to be 100 ns.

As shown in FIG. 11, in the first comparative example, a resistancevalue of the variable resistance layer remains in an initial resistancevalue and does not show any change in its resistance state. Therefore,the variable resistance element according to the first comparativeexample cannot be used as a memory.

Second Comparative Example

The following describes a variable resistance element according to asecond comparative example. A structure of the variable resistanceelement according to the second comparative example is the same as thatof the variable resistance element 10 in the first embodiment.Therefore, the structure of the variable resistance element is notdescribed below.

FIG. 12 is a graph plotting variation of a resistance state of avariable resistance layer included in the variable resistance elementaccording to the second comparative example in the case where both avoltage value Vw1 of a first writing voltage pulse and a voltage valueVw2 of a second writing voltage pulse are the same −3.0 V and both avoltage value Ve1 of a first erasing voltage pulse and a voltage valueVe2 of a second erasing voltage pulse are the same +4.0 V. Here, in anycases, a pulse width is assumed to be 100 ns.

As shown in FIG. 12, in the second comparative example, a resistancestate of the variable resistance layer are varied up to a pulse count of10. However, after that, a difference in a resistance value between alow resistance state and a high resistance state is sometimesconsiderably small. Then, at and after a pulse count of 90, thedifference is always small.

The first and second comparative examples show that a variableresistance element with stable operation cannot be achieved when|Vw1|=|Vw2| and |Ve1|=|Ve2|. On the other hand, the variable resistanceelement 10 according to the first embodiment can achieve stableoperation as shown in FIG. 3.

Second Embodiment

As described above, the driving method according to the first embodimentallows the variable resistance element 10 to have good endurancecharacteristics. However, in very rare cases, writing in a secondwriting step and a second erasing step fail (in other words, thevariable resistance layer is not changed to have a desired resistancestate). A variable resistance element according to a second embodimentof the present invention addresses the above drawback and can achievemore stable operation by executing a recovery writing step and arecovery erasing step when the above failures occurs.

FIG. 13 is a graph plotting an example of variation of a resistancestate of a variable resistance layer by a method of driving the variableresistance element according to the second embodiment of the presentinvention. FIG. 13 shows an example of variation of a resistance stateof the variable resistance layer when the second writing step fails inthe case where, after execution of the first writing step and the firsterasing step, the second writing voltage pulse (having a voltage valueVw2 of −2.0 V and a pulse width of 100 ns) is applied in the secondwriting step and the second erasing voltage pulse (having a voltagevalue Ve2 of +2.5 V and a pulse width of 100 ns) is applied in thesecond erasing step.

A failure in the writing step is detected in a verification step forverifying whether or not the variable resistance layer is in a desiredresistance state after being applying with a voltage pulse (for example,whether or not the variable resistance layer is in the low resistancestate if detection is performed after the second writing step).

In the example shown in FIG. 13, after the writing failure, a recoverywriting voltage pulse (having a voltage value Vw3 of −3.0 V and a pulsewidth of 100 ns) is applied in a recovery writing step, and then arecovery erasing voltage pulse (having a voltage value Ve3 of +4.0 V anda pulse width of 100 ns) is applied in a following recovery erasingstep. Here, an absolute value of the voltage value Vw3 of the recoverywriting voltage pulse is greater than an absolute value of the voltagevalue Vw2 of the second writing voltage pulse, and an absolute value ofthe voltage value Ve3 of the recovery erasing voltage pulse is greaterthan an absolute value of the voltage value Ve2 of the second erasingvoltage pulse. For example, as shown in FIG. 13, it is possible thatVw3=Vw1 and Ve3=Ve1.

By referring to FIG. 13, it is confirmed that, after writing failure,the recovery writing voltage pulse having the same voltage value as thatof the first writing voltage pulse and the recovery erasing voltagepulse having the same voltage value as that of the first erasing voltagepulse are applied, which results in following stable variation of theresistance state.

The above-described method of driving the variable resistance elementaccording to the second embodiment of the present invention is presentedby a flowchart of FIG. 14. First, a first writing step is executed byapplying a voltage pulse having a voltage value Vw1 (S101). Thereby, thestate of the variable resistance layer 3 is changed from an initial highresistance state (HR) to a low resistance state (LR). Next, a firsterasing step is executed by applying a voltage pulse having a voltagevalue Ve1 (S102). Thereby, the state of the variable resistance layer ischanged from the low resistance state to a high resistance state.

After that, Step S113 for repeating a set of a second writing step, averification step, and a second erasing step is executed. Morespecifically, Step S113 is repetition of a set of: the second writingstep (S103A) using a voltage pulse of a voltage value Vw2; theverification step (S103C) using a readout voltage that is too low tochange the resistance state of the variable resistance layer; and thesecond erasing step (S103B) using a voltage pulse of a voltage valueVet.

In the verification step (S103C), it is verified whether or not thevariable resistance layer is in a desired resistance state, by applyinga read voltage to the variable resistance element and comparing acurrent value of current flowing in the variable resistance element to athreshold value.

If the verification step detects that the variable resistance layer isnot in the desired low resistance state (NG at S103C), then a recoverywriting step is executed using a voltage pulse of a voltage value Vw3(for example, Vw3=Vw1) (S104). Thereby, the state of the variableresistance layer is changed from the high resistance state (HR) to thelow resistance state (LR). Next, a recovery erasing step is executedusing a voltage pulse of a voltage value Ve3 (for example, Ve3=Ve1)(S105). Thereby, the state of the variable resistance layer is changedfrom the low resistance state to the high resistance state.

Then, Step S113 is executed to repeat the set of the second writingstep, the verification step, and the second erasing step.

By the above-described driving method, as seen from FIG. 13, if writingof the second writing step fails, the recovery writing step and therecovery erasing step are executed to cause desired variation of theresistance state in following the second writing steps and the seconderasing steps.

It should be noted that it has been described as an example in the abovedescription that a verification step is provided to verify writing inthe second writing step (in other words, verify whether or not thevariable resistance layer is in the low resistance state). However, itis also possible to provide a different verification step for verifyingwriting in the second erasing step (in other words, verify whether ornot the variable resistance layer is in the high resistance state).

In this case, if the verification step after the second erasing stepdetects that the variable resistance layer is not in the high resistancestate, then the recovery erasing step is first executed and then therecovery writing step is executed.

Third Embodiment

The third embodiment according to the present invention is a nonvolatilestorage device that includes the variable resistance elements describedin the first embodiment. The following describes a structure andoperations of the nonvolatile storage device.

[Structure of Nonvolatile Storage Device]

FIG. 15 is a block diagram showing an example of the structure of thenonvolatile storage device according to the third embodiment of thepresent invention. As shown in FIG. 15, the nonvolatile storage device200 includes a memory array 201, an address buffer 202, a control unit203, a row decoder 204, a word line driver 205, a column decoder 206,and a bit line/plate line driver 207. The memory array 201 includes thevariable resistance elements. Here, a set of the control unit 203, theword line driver 205, and the bit line/plate line driver 207 is called adrive unit 208.

As shown in FIG. 15, the memory array 201 includes: two word lines W201and W202; two bit lines B201 and B202; two plate lines P201 and P202;four transistors T211, T212, T221, and T222; and memory cells MC211,MC212, MC221, and MC222. The word lines W201 and W202 are arranged in avertical direction. The bit lines B201 and B202 are arranged in ahorizontal direction and cross the word lines W201 and W202. The platelines P201 and P202 are arranged in a horizontal direction andcorrespond to the bit lines B201 and B202, respectively. The transistorsT211, T212, T221, and T222 are arranged in a matrix and each of thetransistors corresponds to a corresponding one of intersections of theword lines W201 and W202 and the bit lines B201 and B202. The memorycells MC211, MC212, MC221, and MC222 are arranged in a matrix and eachof the memory cells corresponds to a corresponding one of thetransistors T211, T212, T221, and T222.

The number of each of the above-described structure elements is notlimited to the above. For instance, although it has been described as anexample that the memory array 201 has four memory cells, the memoryarray 201 may have five or more memory cells.

Each of the above-described memory cells MC211, MC212, MC221, and MC222is the variable resistance element described in the first embodimentwith reference to FIG. 4. With reference also to FIG. 4, a structure ofthe memory array 201 is described in detail below. The transistor T211and the memory cell MC211 are provided between the bit line B201 and theplate line P201. Here, a source of the transistor T211 and the firstterminal 11 of the memory cell MC211 are arranged in series to beconnected to each other. The structure is explained in more detailbelow. The transistor T211 is arranged between the bit line B201 and thememory cell MC211 and connected to the bit line B201 and the memory cellMC211. The memory cell MC211 is arranged between the transistor T211 andthe plate line P201 and connected to the transistor T211 and the plateline P201. A gate of the transistor T211 is connected to the word lineW201.

The other three transistors T212, T221, and T22 are arranged in serieswith the other three memory cells MC212, MC221, and MC222, respectively,and they are connected in the same manner as described for thetransistor T211 and the memory cell MC211. Therefore, the connectionstructure is not explained again.

With the above structure, when gates of the transistors T211, T212,T221, and T22 are applied with a predetermined voltage (activationvoltage) via the word lines W201 and W202, drains and sources of thetransistors T211, T212, T221, and T22 are conducted.

The address buffer 202 receives address signals ADDRESS from an externalcircuit (not shown), and then, based on the received address signalsADDRESS, provides row address signals ROW to the row decoder 204 andcolumn address signals OLUMN to the column decoder 206. The addresssignals ADDRESS are signals indicating an address of a memory cellselected from the memory cells MC211, MC212, MC221, and MC222. The rowaddress signals ROW are signals indicating an address of a row of theaddress indicated in the address signals ADDRESS. The column addresssignals COLUMN are signals indicating an address of a column of theaddress indicated in the address signals ADDRESS.

The control unit 203 selects at least one of a write mode, a reset mode,and a read mode, based on a mode selection signal MODE received from anexternal circuit.

In the write mode, the control unit 203 issues a control signal CONTinstructing to “apply a writing voltage”, to the bit line/plate linedriver 207, based on input data Din received from an external circuit.

In the case of the read mode, the control unit 203 issues a controlsignal CONT instructing to “apply a read voltage”, to the bit line/plateline driver 207. In the read mode, the control unit 203 further receivesa signal I_(READ) from the bit line/plate line driver 207, and providesthe external circuit with output data Dout indicating a bit valuecorresponding to the signal I_(READ). The signal I_(READ) is a signalindicating a current value of current flowing in the plate lines P201and P202 in the read mode.

In the reset mode, the control unit 203 detects a memory state of eachof the memory cells MC211, MC212, MC221, and MC222, and based on thememory state, issues the control signal CONT instructing to “apply areset voltage”, to the bit line/plate line driver 207.

The row decoder 204 receives the row address signals ROW from theaddress buffer 202, and based on the row address signals ROW, selectsone of the two word lines W201 and W202. Based on the output signal ofthe row decoder 204, the word line driver 205 applies an activationvoltage to the word line selected by the row decoder 204.

The column decoder 206 receives the column address signals COLUMN fromthe address buffer 202, and based on the column address signals COLUMN,selects one of the two bit lines B201 and B202 and also selects one ofthe two plate lines P201 and P202.

When the bit line/plate line driver 207 receives the control signal CONTinstructing to “apply the writing voltage” from the control unit 203,the bit line/plate line driver 207 applies the writing voltage V_(WRITE)to the bit line selected by the column decoder 206 and sets the plateline selected by the column decoder 206 to be grounded, based on theoutput signal of the column decoder 206.

When the bit line/plate line driver 207 receives the control signal CONTinstructing to “apply the read voltage” from the control unit 203, thebit line/plate line driver 207 applies the read voltage V_(READ) to thebit line selected by the column decoder 206 and sets the plate lineselected by the column decoder 206 to be grounded, based on the outputsignal of the column decoder 206. Then, the bit line/plate line driver207 provides the control unit 203 with a signal I_(READ) indicating thecurrent value of current flowing in the selected plate line.

When the bit line/plate line driver 207 receives the control signal CONTinstructing to “apply the reset voltage” from the control unit 203, thebit line/plate line driver 207 applies the reset voltage V_(RESET) tothe bit line selected by the column decoder 206 and sets the plate lineselected by the column decoder 206 to be grounded, based on the outputsignal of the column decoder 206.

Here, the voltage value of the writing voltage V_(WRITE) is set to −3.5V for a first writing step and −2.5 V for a second writing step, and apulse width of the writing voltage V_(WRITE) is set to 100 ns, forexample. Further, the voltage value of the read voltage V_(READ) is setto +0.5 V, for example. Furthermore, the voltage value of the resetvoltage V_(RESET) is set to +4.0 V for a first erasing step and +2.5 Vfor a second erasing step, and a pulse width of the reset voltageV_(RESET) is set to 100 ns, for example.

Such various voltage pulses having different voltage values aregenerated by using a voltage generation circuit (not shown) that cangenerate various kinds of voltages. An example of methods fordetermining the voltage value of the voltage pulse to be generated isdescribed in detail in the following operation example.

[Operations of Nonvolatile Storage Device]

The operation example of the nonvolatile storage device 200 having theabove-described structure is described for each of: the write mode (modefor writing input data Din to a memory cell); the reset mode (mode forresetting the data written in a memory cell); and the read mode (modefor outputting the data written in a memory cell from the memory asoutput data Dout). Here, the first writing step and the second writingstep correspond to the write modes, and the first erasing step and thesecond erasing step correspond to the reset modes.

For convenience in the explanation, it is assumed that the modeselection signal MODE includes information designating whether the writemode corresponds to the first writing step or the second writing step,and designating whether the reset mode corresponds to the first erasingstep or the second erasing step. Via the mode selection signal MODE, anexternal circuit instructs the control unit 203 of which of the firstwriting step, the second writing step, the first erasing step, and thesecond erasing step is to be executed.

It is also assumed that the address signals ADDRESS are the signalindicating an address of the memory cell MC211.

[Write Mode]

The control unit 203 receives input data Din from an external circuit.Here, if the input data Din is “1”, then the control unit 203 issues thecontrol signal CONT instructing to “apply the writing voltage” to thebit line/plate line driver 207. On the other hand, if the input data Dinis “0”, then the control unit 203 does not issues the control signalCONT.

The control signal CONT instructing to “apply the writing voltage”includes information indicating which of the first writing voltage pulseand the second wring voltage pulse is to be applied to a target memorycell according to the designation of the mode selection signal MODE.

When the bit line/plate line driver 207 receives the control signal CONTinstructing to “apply the writing voltage” from the control unit 203,the bit line/plate line driver 207 applies the writing voltage V_(WRITE)to the bit line B201 selected by the column decoder 206. In addition,the bit line/plate line driver 207 sets the plate line P201 selected bythe column decoder 206, to be grounded.

Here, the word line W201 selected by the row decoder 204 is applied withan activation voltage by the word line driver 205. Therefore, the drainand the source of the transistor T211 are conducted.

Thereby, in the first writing step, the first writing voltage pulsehaving a voltage value of −3.5 V and a pulse width of 100 ns is appliedto the memory cell MC211 as the writing voltage V_(WRITE). Then, in thesecond writing step, the second writing voltage pulse having a voltagevalue of −2.5 V and a pulse width of 100 ns is applied to the memorycell MC211 as the writing voltage V_(WRITE). Thereby, the state of thememory cell MC211 is changed from the high resistance state to the lowresistance state. On the other hand, no writing voltage pulse is appliedto the memory cells M221 and MC222, and no activation voltage is appliedto the gate of the transistor T212 connected in series with the memorycell MC212. As a result, the resistance states of the memory cellsMC212, MC221, and MC222 are not changed.

In the above manner, only the memory cell MC211 can be changed to thelow resistance state, which allows one bit data indicating “1”corresponding to the low resistance state to be written in the memorycell MC211.

When the writing to the memory cell MC211 has been completed, newaddress signals ADDRESS are provided to the address buffer 202, and theabove-described operation of the write mode of the nonvolatile storagedevice is repeated for the other memory cells except the memory cellMC211.

[Read Mode]

The control unit 203 issues a control signal CONT instructing to “applythe read voltage” to the bit line/plate line driver 207.

When the bit line/plate line driver 207 receives the control signal CONTinstructing to “apply the read voltage” from the control unit 203, thebit line/plate line driver 207 applies the read voltage V_(READ) to thebit line B201 selected by the column decoder 206. In addition, the bitline/plate line driver 207 sets the plate line P201 selected by thecolumn decoder 206 to be grounded.

Here, the word line W201 selected by the row decoder 204 is applied withan activation voltage by the word line driver 205. Therefore, the drainand the source of the transistor T211 are conducted.

Thereby, as the read voltage V_(READ), a measuring voltage of +0.5 V isapplied to the memory cell MC211. As a result, current having a currentvalue depending on the resistance value of the memory cell MC211 flowsinto the plate line P201 via the memory cell MC212.

Here, no measured voltage is applied to the memory cells MC221 andMC222, and no activation voltage is applied to the gate of thetransistor T212 connected in series with the memory MC212. Therefore,the above current does not flow in the memory cells MC212, MC221, andMC222.

Next, the bit line/plate line driver 207 measures a current value ofcurrent flowing in the plate line P201, and provides the control unit203 with the signal I_(READ) indicating a value of the measurement.

The control unit 203 provide the outside with output data Dout dependingon a current value indicated by the signal I_(READ). For example, if thecurrent value indicated by the signal I_(READ) is a current value ofcurrent flowing at the time when the memory cell MC211 is in the lowresistance state, then the control unit 203 outputs output data Doutindicating “1”.

Thereby, current depending on the resistance value of the memory cellMC211 flows only to the memory cell MC211 and then to the plate lineP201. As a result, one bit data indicating “1” is read out from thememory cell MC211 (in other words, one bit data is read out).

When the readout from the memory cell MC211 has been completed, newaddress signals ADDRESS are provided to the address buffer 202, and theabove-described operation of the read mode of the nonvolatile storagedevice is repeated for the other memory cells except the memory cellMC211.

[Reset Mode]

In the reset mode, first, the control unit 203 executes theabove-described read mode to obtain information of a state of aresistance value (here, memory state) of the memory cell MC211. Then, ifit is determined that one bit data indicating “1” is stored in thememory cell MC211 (in other words, if it is determined that the memorycell MC211 is in the low resistance state), then the control unit 203issues the control signal CONT instructing to “apply the reset voltage”to the bit line/plate line driver 207. On the other hand, if it isdetermined that one bit data indicating “0” is stored in the memory cellMC211 (in other words, if it is determined that the memory cell MC211 isin the high resistance state), then the control unit 203 does not issuesthe above control signal CONT.

The control signal CONT instructing to “apply the reset voltage”includes information indicating which of the first erasing voltage pulseand the erasing wring voltage pulse is to be applied to a target memorycell according to the designation of the mode selection signal MODE.

When the bit line/plate line driver 207 receives the control signal CONTinstructing to “apply the reset voltage” from the control unit 203, thebit line/plate line driver 207 applies the reset voltage V_(RESET) tothe bit line 8201 selected by the column decoder 206. In addition, thebit line/plate line driver 207 sets the plate line P201 selected by thecolumn decoder 206, to be grounded.

Here, the word line W201 selected by the row decoder 204 is applied withan activation voltage by the word line driver 205. Therefore, the drainand the source of the transistor T211 are conducted.

Therefore, in the first erasing step, the first erasing voltage pulsehaving a voltage value of +4.0 V and a pulse width of 100 ns is appliedto the memory cell MC211 as the reset voltage V_(RESET). Then, in thesecond erasing step, the second erasing voltage pulse having a voltagevalue of +2.5 V and a pulse width of 100 ns is applied to the memorycell MC211 as the reset voltage V_(RESET). Thereby, the state of thememory cell MC211 is changed from the low resistance state to the highresistance state. On the other hand, no erasing voltage pulse is appliedto the memory cells M221 and MC222, and no activation voltage is appliedto the gate of the transistor T212 connected in series with the memorycell MC212. As a result, the resistance states of the memory cellsMC212, MC221, and MC222 are not changed.

In the above manner, only the memory cell MC211 can be changed to thehigh resistance state, which allows one bit data indicating “1”corresponding to the low resistance state to be reset to “0”corresponding to the high resistance state.

When the resetting of the memory cell MC211 has been completed, newaddress signals ADDRESS are provided to the address buffer 202, and theabove-described operation of the reset mode of the nonvolatile storagedevice is repeated for the other memory cells except the memory cellMC211.

As described above, the nonvolatile storage device 200 sets in theprogram mode, an absolute value of the voltage value of the firstwriting voltage pulse to be greater than an absolute value of thevoltage value of the second writing voltage pulse, and sets, in thereset mode, an absolute value of the voltage value of the first erasingvoltage pulse to be greater than an absolute value of the voltage valueof the second erasing voltage pulse. Thereby, stable high-speedoperation and good endurance characteristics can be achieved.

It is also possible as a different structure that the nonvolatilestorage device automatically executes the first writing step and thefirst erasing step as initialization for all memory cells.

In such a nonvolatile storage device, the control unit further includes:a flag register that indicates whether the initialization has beencompleted; and an address counter that can designate all memory cellssequentially, for example.

The control unit executes the first writing step and the first erasingstep for each of the memory cells sequentially designated by the addresscounter, and then updates a value in the flag register to indicate thecompletion of the initialization. Then, according to access from anexternal circuit, the control unit executes the second writing step andthe second erasing step.

Fourth Embodiment

The fourth embodiment of the present invention is a cross-point typenonvolatile storage device having the variable resistance elementsdescribed in the first embodiment. Here, the cross-point typenonvolatile storage device is a storage device in which an active layeris provided at an intersection (three-dimensional intersection) of aword line and a bit line.

The following describes a structure and operations of the nonvolatilestorage device according to the fourth embodiment.

[Structure of Nonvolatile Storage Device]

FIG. 16 is a block diagram showing an example of a structure of thenonvolatile storage device according to the fourth embodiment of thepresent invention. As shown in FIG. 16, the cross-point type nonvolatilestorage device 100 includes a memory array 101, an address buffer 102, acontrol unit 103, a row decoder 104, a word line driver 105, a columndecoder 106, and a bit line/plate line driver 107. The memory array 101includes the variable resistance elements. Here, a set of the controlunit 103, the word line driver 105, and the bit line/plate line driver107 is called a drive unit 108.

As shown in FIG. 16, the memory array 101 includes a plurality of wordlines W101, W102, W103, . . . and a plurality of bit lines B101, 8102,B103, . . . . The word lines W101, W102, W103, . . . are arranged inparallel in a vertical direction. The bit lines B101, B102, B103, . . .are arranged in parallel in a horizontal direction and cross the wordlines W101, W102, W103, . . . . Furthermore, the word lines W101, W102,W103, . . . are arranged on a first plane in parallel to a main plane ofa substrate (not shown), and the bit lines B101, B102, B103, . . . arearranged on a second plane that is above the first plane and insubstantially parallel to the first plane. Therefore, the word linesW101, W102, W103, . . . cross the bit lines B101, B102, B103, . . .three-dimensionally. At the three-dimensional intersections, there areprovided a plurality of memory cells MC111, MC112, MC113, MC121, MC122,MC123, MC131, MC132, MC133, . . . (hereinafter, referred to as “memorycells MC111, MC112, . . . ”).

In each of the memory cells MC, a variable resistance element isconnected in series with a corresponding one of the current steeringelements D111, D112, D113, D121, D122, D123, D131, D132, D133 each ofwhich is implemented as a bidirectional diode. In addition, each of thevariable resistance elements is also connected to a corresponding one ofthe bit lines 8101, B102, B103, . . . . Moreover, each of the currentsteering elements is connected to (a) a corresponding variableresistance element and (b) a corresponding one of the word lines W101,W102, W103, . . . . The variable resistance element may be the variableresistance element 10 according to the first embodiment.

The address buffer 102 receives address signals ADDRESS from an externalcircuit (not shown), and then, based on the received address signalsADDRESS, provides row address signals ROW to the row decoder 104 andcolumn address signals COLUMN to the column decoder 106. The addresssignals ADDRESS are signals indicating an address of a memory cellselected from the memory cells MC112, MC121, . . . . The row addresssignals ROW are signals indicating an address of a row of the addressindicated in the address signals ADDRESS. The column address signalsCOLUMN are signals indicating an address of a column of the addressindicated in the address signals ADDRESS.

The control unit 103 selects one of a program mode (corresponding to thefirst and second writing steps and the first and second erasing steps)and an read mode, based on a mode selection signal MODE received from anexternal circuit.

In the program mode, the control unit 103 applies a write voltage pulseor an erasing voltage pulse to the word line driver 105, based on inputdata Din received from an external circuit.

Then, in the read mode, the control unit 103 applies a readout voltageto the word line driver 105. In the read mode, the control unit 103further receives a signal I_(READ) from the word line driver 105, andprovides the external circuit with output data Dout indicating a bitvalue depending on the signal I_(READ). The signal I_(READ) is a signalindicating a current value of current flowing in the word lines W101,W102, W103, . . . during the read mode.

The row decoder 104 receives the row address signals ROW from theaddress buffer 102, and based on the row address signals ROW, selectsone of the word lines W101, W102, W103, . . . . Based on the outputsignal of the row decoder 104, the word line driver 105 applies anactivation voltage to the word line selected by the row decoder 104.

The column decoder 106 receives the column address signals COLUMN fromthe address buffer 102, and selects one of the bit lines B101, B102,B103, . . . based on the column address signals COLUMN.

The bit line driver 107 sets the bit line selected by the column decoder106, to be grounded, based on the output signal of the column decoder106.

It should be noted that the fourth embodiment provides a cross-pointtype storage device that is made of a single layer, but the cross-pointtype storage device may be made of multiple layers by stacking memoryarrays.

It should also be noted that a positional relationship may be exchangedbetween the variable resistance element and the current steeringelement. More specifically, it is also possible that the word lines areconnected to the variable resistance elements and the bit lines areconnected to the current steering elements.

It is also possible that one or both of a bit line and a word linesupplies power to a variable resistance element. In more detail, it ispossible that one of a bit line and a word line is grounded and theother line that is not grounded applies a power voltage to the variableresistance element. Or, it is also possible that both of a bit line anda word line are applied with different power voltages other than aground voltage, and power is supplied to the variable resistance elementbased on a predetermined voltage difference between the bit line and theword line.

[Operations of Nonvolatile Storage Device]

The operation example of the nonvolatile storage device 100 having theabove-described structure is described for each of the program mode andthe read mode. Here, since known methods can be used for selecting a bitline or a word line and for applying a voltage pulse, the methods arenot described in detail below.

For convenience in the explanation, it is assumed that a mode selectionsignal MODE includes information designating whether the program modecorresponds to the first writing step, the second writing step, thefirst erasing step, or the second erasing step. Using the mode selectionsignal MODE, An external circuit instructs the control unit 103 which ofthe first writing step, the second writing step, the first erasing step,and the second erasing step is to be executed.

In the following, it is assumed that programming and reading areexecuted for the memory cell MC122.

[Program Mode]

When one bit data indicating “1” is to be programed (written) in thememory cell MC122, the bit line driver 107 sets the bit line B102 to begrounded and the word line driver 105 electrically connects the wordline W102 to the control unit 103. Then, the control unit 103 performscontrol to apply a writing voltage pulse to the word line W102. Here, avoltage value of the writing voltage pulse is set to be −3.5 V in thefirst writing step and −2.5 V in the second writing step, respectively,according to the designation of the mode selection signal MODE. Inaddition, a pulse width is set to be 100 ns in both steps.

The above-described operation allows the writing voltage pulse to beapplied to the variable resistance element in the memory cell MC122. Asa result, the state of the variable resistance element in the memorycell MC122 is changed to the low resistance state corresponding to “1”.

On the other hand, when one bit data indicating “0” is to be programed(erased) in the memory cell MC122, the bit line driver 107 sets the bitline B102 to be grounded and the word line driver 105 electricallyconnects the word line W102 to the control unit 103.

Then, the control unit 103 performs control to apply an erasing voltagepulse to the word line W102. Here, a voltage value of the erasingvoltage pulse is set to be +4.0 V in the first erasing step and +2.5 Vin the second writing step, respectively, according to the designationof the mode selection signal MODE. In addition, a pulse width is set tobe 100 ns in both steps.

The above-described operation allows a erasing voltage pulse to beapplied to the variable resistance element in the memory cell MC122. Asa result, the state of the variable resistance layer in the memory cellMC122 is changed to the high resistance state corresponding to “0”.

[Read Mode]

When data is to be read out from the memory cell MC122, the bit linedriver 107 sets the bit line B102 to be grounded and the word linedriver 105 electrically connects the word line W102 to the control unit103. Then, the control unit 103 performs control to apply a readoutvoltage to the word line W102. Here, a voltage value of the readoutvoltage is set to be +0.5 V.

When the readout voltage is applied to the memory cell MC122, currenthaving a current value depending on a resistance value of the variableresistance layer in the memory cell MC122 flows between the bit lineB102 and the word line W102. The control unit 103 detects the currentvalue of the current, and detects the resistance state of the memorycell MC122 based on the current value and the readout voltage.

If the variable resistance layer in the memory cell MC122 is in the lowresistance state, then it is determined that the data written in thememory cell MC122 is “1”. On the other hand, if the variable resistancelayer in the memory cell MC122 is in the high resistance state, then itis determined that the data written in the memory cell MC122 is “0”.

As described above, in the program mode, the nonvolatile storage device100 sets an absolute value of a voltage value of the first writingvoltage pulse to be greater than an absolute value of a voltage value ofthe second writing voltage pulse, and sets an absolute value of avoltage value of the first erasing voltage pulse to be greater than anabsolute value of a voltage value of the second erasing voltage pulse.Thereby, stable high-speed operation and good endurance characteristicscan be achieved.

Likewise the nonvolatile storage device according to the previousembodiment, the nonvolatile storage device according to the fourthembodiment may automatically execute the first writing step and thefirst erasing step as initialization for all memory cells.

Other Embodiments

It should be noted that it has been described in each of the aboveembodiments that the variable resistance layer is made of stackedtantalum oxide layers, but the present invention is not limited to theabove. For example, the variable resistance layer may be made of stackedhafnium (Hf) oxide layers, or stacked zirconium (Zr) oxide layers.

When the variable resistance layer is made of stacked hafnium oxidelayers, the following is preferable. Assuming that a composition of afirst hafnium oxide layer is expressed as HfO_(x) and a composition of asecond hafnium oxide layer is expressed as HfO_(y), x is within a rangeapproximately from 0.9 to 1.6, y is within a range approximately from1.89 to 1.97, and the first and second hafnium oxide layers areoxygen-deficient compositions in comparison with stoichiometriccompositions.

When the variable resistance layer is made of stacked zirconium oxidelayers, the following is preferable. Assuming that a composition of afirst zirconium oxide layer is expressed as ZrO_(x) and a composition ofa second zirconium oxide layer is expressed as ZrO_(y), x is within arange approximately from 0.9 to 1.4, y is within a range approximatelyfrom 1.8 to 2, and the first and second zirconium oxide layers areoxygen-deficient compositions in comparison with stoichiometriccompositions.

The above-described oxygen-deficient hafnium oxides and oxygen-deficientzirconium oxides can be generated in the same method as that for theabove-described oxygen-deficient tantalum oxides described in the aboveembodiments.

It should be noted that a composition of a transition metal oxide can beanalyzed by using Auger Electron Spectroscopy (AES), X-ray PhotoelectronSpectroscopy (XPS), Rutherford Backscattering Spectrometry (RBS), andthe like, and the best method for analyzing absolute values ofcompositions most precisely is the RBS. Regarding the above-describedhafnium oxide and zirconium oxide, the RBS is used for the compositionanalysis for each of the transition metal oxides.

INDUSTRIAL APPLICABILITY

The variable resistance element driving method and the nonvolatilestorage device according to the present invention are useful as variableresistance element driving methods and storage devices, respectively,which are utilized in various electronic devices such as personalcomputers and mobile telephones.

NUMERICAL REFERENCES

-   1 substrate-   2 lower electrode-   3 variable resistance layer-   3 a first tantalum oxide layer-   3 b second tantalum oxide layer-   4 upper electrode-   5 power source-   10 variable resistance element-   11 first terminal-   12 second terminal-   100 nonvolatile storage device-   101 memory array-   102 address buffer-   103 control unit-   104 row decoder-   105 word line driver-   106 column decoder-   107 bit line driver-   108 drive unit-   W101, W102, W103 word lines-   B101, B102, B103 bit lines-   MC111, MC112, MC113, MC121, MC122, MC123, MC131, MC132, MC133 memory    cells-   D111, D112, D113, D121, D122, D123, D131, D132, D133    current-limiting elements-   200 nonvolatile storage-   201 memory array-   202 address buffer-   203 control unit-   204 row decoder-   205 word line driver-   206 column decoder-   207 bit line/plate line driver-   208 drive unit-   W210, W202 word lines-   B201, B202 bit lines-   P201, P202 plate lines-   MC211, MC212, MC221, MC222 memory cells-   T211, T212, T221, T222 transistors

1. A method of driving a variable resistance element that includes ametal oxide having a resistance value increased and decreased dependingon application of electric pulses, the metal oxide comprising a firstoxide layer and a second oxide layer which are stacked, the second oxidelayer having an oxygen content percentage higher than an oxygen contentpercentage of the first oxide layer, said method comprising: performinga plurality of writing steps by applying a writing voltage pulse havinga first polarity to the metal oxide, so as to change a resistance stateof the metal oxide from high to low; and performing a plurality oferasing steps by applying an erasing voltage pulse having a secondpolarity to the metal oxide, so as to change the resistance state of themetal oxide from low to high, the second polarity being different fromthe first polarity, wherein |Vw1|>|Vw2| is satisfied, where Vw1represents a voltage value of the writing voltage pulse for first toN-th writing steps among the plurality of writing steps, where N isequal to or more than 1, and Vw2 represents a voltage value of thewriting voltage pulse for (N+1)-th and subsequent writing steps amongthe plurality of writing steps, |Ve1|>|Ve2| is satisfied, where Ve1represents a voltage value of the erasing voltage pulse for first toM-th erasing steps among the plurality of erasing steps, where M isequal to or more than 1, and Ve2 represents a voltage value of theerasing voltage pulse for (M+1)-th and subsequent erasing steps amongthe plurality of erasing steps, and the (N+1)-th writing step followsthe M-th erasing step.
 2. The method according to claim 1, wherein|Ve1|≧|Vw1| and |Ve2|≧|Vw2| are further satisfied.
 3. The methodaccording to claim 1, further comprising: performing a recovery writingstep by applying a recovery writing voltage pulse having a voltage valueof Vw3, where |Vw3|>|Vw2|, to the metal oxide, so as to change theresistance state of the metal oxide from high to low, when any one ofthe (N+1)-th and subsequent writing steps fails to change the resistancestate of the metal oxide from high to low; and performing a recoveryerasing step by applying a recovery erasing voltage pulse having avoltage value of Ve3, where |Ve3|>|Ve2|, to the metal oxide, so as tochange the resistance state of the metal oxide from low to high, whenany one of the (M+1)-th and subsequence erasing steps fails to changethe resistance state of the metal oxide from low to high.
 4. The methodaccording to claim 3, wherein the voltage value of Vw1 is equal to thevoltage value of Vw3, and the voltage value of Ve1 is equal to thevoltage value of Ve3.
 5. The method according to claim 1, wherein thefirst oxide layer comprises a tantalum oxide having a compositionrepresented by TaO_(x), where 0.8≦x≦1.9, and the second oxide layercomprises a tantalum oxide having a composition represented by TaO_(y),where 2.1≦y<2.5.
 6. A nonvolatile storage device comprising: a firstelectrode; a second electrode; a variable resistance element which isprovided between said first electrode and said second electrode andwhich includes a metal oxide having a resistance value increased anddecreased depending on application of an electric pulse between saidfirst electrode and said second electrode; and a drive unit, whereinsaid metal oxide comprises a first oxide layer and a second oxide layerwhich are stacked, said second oxide layer having an oxygen contentpercentage higher than an oxygen content percentage of said first oxidelayer, and said drive unit is configured to perform: a writing step byapplying a writing voltage pulse having a first polarity between saidfirst electrode and said second electrode, so as to change a resistancestate of said metal oxide from high to low; and an erasing step byapplying an erasing voltage pulse having a second polarity between saidfirst electrode and said second electrode, so as to change theresistance state of said metal oxide from low to high, the secondpolarity being different from the first polarity, wherein |Vw1|>|Vw2| issatisfied, where Vw1 represents a voltage value of the writing voltagepulse for first to N-th writing steps, where N is equal to or more than1, and Vw2 represents a voltage value of the writing voltage pulse for(N+1)-th and subsequent writing steps, |Ve1|>|Ve2| is satisfied, whereVe1 represents a voltage value of the erasing voltage pulse for firstand M-th erasing steps, where M is equal to or more than 1, and Ve2represents a voltage value of the erasing voltage pulse for (M+1)-th andsubsequent erasing steps, and the (N+1)-th writing step follows the M-therasing step.
 7. The nonvolatile storage device according to claim 6,wherein |Ve1|≧|Vw1| and |Ve2|≧|Vw2| are further satisfied.
 8. Thenonvolatile storage device according to claim 6, wherein said drive unitis configured to further perform: a recovery writing step by applying arecovery writing voltage pulse having a voltage value of Vw3, where|Vw3|>|Vw2|, between said first electrode and said second electrode, soas to change the resistance state of said metal oxide from high to low,when any one of the (N+1)-th and subsequence writing steps fails tochange the resistance state of said metal oxide from high to low; and arecovery erasing step by applying a recovery erasing voltage pulsehaving a voltage value of Ve3, where |Ve3|>|Ve2|, between said firstelectrode and said second electrode, so as to change the resistancestate of said metal oxide from low to high, when any one of the (M+1)-thand subsequent erasing step fails to change the resistance state of saidmetal oxide from low to high.
 9. The nonvolatile storage deviceaccording to claim 8, where the voltage value of Vw1 is equal to thevoltage value of Vw3, and the voltage value of Ve1 is equal to thevoltage value of Ve3.
 10. The nonvolatile storage device according toclaim 6, wherein said first oxide layer comprises a tantalum oxidehaving a composition represented by TaO_(x), where 0.8≦x≦1.9, and saidsecond oxide layer comprises a tantalum oxide having a compositionrepresented by TaO_(y), where 2.1≦y<2.5.
 11. The nonvolatile storagedevice according to claim 6, further comprising a current steeringelement electrically connected to one of said first electrode and saidsecond electrode.
 12. The nonvolatile storage device according to claim11, wherein said current steering element is a selection transistor. 13.The nonvolatile storage device according to claim 11, wherein saidcurrent steering element is a diode.
 14. An initialization method ofperforming initialization for a variable resistance element whichincludes a metal oxide having a resistance value increased and decreaseddepending on application of electric pulses, the metal oxide including afirst oxide layer and a second oxide layer which are stacked, the secondoxide layer having an oxygen content percentage higher than an oxygencontent percentage of the first oxide layer, to and from the variableresistance element, data being written and erase by performing one ormore times a set of a writing step and an erasing step so as to performat least one writing step and at least one erasing steps, the writingstep being performed by applying a writing voltage pulse having a firstpolarity and a voltage value of Vw2 to the metal oxide, so as to changea resistance state of the metal oxide from high to low, and the erasingstep being performed by applying an erasing voltage pulse having asecond polarity and a voltage value of Ve2 to the metal oxide, so as tochange the resistance state of the metal oxide from low to high, thesecond polarity being different from the first polarity, and the erasingstep following the writing step, said method comprising: at least oneinitial writing step by applying a voltage pulse having the firstpolarity and a voltage value of Vw1, where |Vw1|>|Vw2|, to the metaloxide, so as to change the resistance state of the metal oxide from highto low; and at least one initial erasing step by applying a voltagepulse having the second polarity and a voltage value of Ve1, where|Ve1|>|Ve2|, to the metal oxide, so as to change the resistance state ofthe metal oxide from low to high, wherein a first one of the at leastone writing step is performed next to a last one of the at least oneinitial erasing step.